System and method for adaptive multiple read of nand flash

ABSTRACT

A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application is a continuation of U.S. patent applicationSer. No. 15/723,041, filed on October 2, 2017, now U.S. Pat. No.10,417,087, issued on Sep. 17, 2019, entitled “SYSTEM AND METHOD FORADAPTIVE MULTIPLE READ OF NAND FLASH”, which (i) claims priority to andthe benefit of U.S. Provisional Application No. 62/403,610, filedOctober 3, 2016, entitled “METHOD OF ADAPTIVE MULTIPLE-READ FOR NANDFLASH”, and which (ii) is a continuation-in-part of U.S. patentapplication Ser. No. 15/230,075, filed on Aug. 5, 2016, now U.S. Pat.No. 10,216,572, issued on Feb. 26, 2019, entitled “FLASH CHANNELCALIBRATION WITH MULTIPLE LOOKUP TABLES”, (“the '075 Application”),which is a continuation-in-part of U.S. patent application No.14/806,063, filed Jul. 22, 2015, entitled “METHOD OF FLASH CHANNELCALIBRATION WITH MULTIPLE LUTS FOR ADAPTIVE MULTIPLE-READ”, which claimspriority to and the benefit of U.S. Provisional Application No.62/027,683, filed Jul. 22, 2014, entitled “METHOD OF FLASH CHANNELCALIBRATION WITH MULTIPLE LUTS FOR ADAPTIVE MULTIPLE-READ”; the entirecontents of all of the above-identified documents are herebyincorporated herein by reference.

FIELD

One or more aspects of embodiments according to the present inventionrelate to flash memory, and more particularly to a system and method foradaptive multiple read of NAND flash memory.

BACKGROUND

As the feature size of lithographic geometry for NAND flash chips isdecreased, the number of electrons that can be used in storage may alsobe reduced, and assuring accurate information storage may become morechallenging. Moreover, reductions in feature size may increase the riskof inter-cell interference. High-capacity NAND flash memory may achievehigh density storage by using multi-level cells (two bits/cell formulti-level cell (MLC) or three bits/cell for triple level cell (TLC))to store more than one bit per cell. Four levels or eight levels or moremay be used. A large number of levels (and small voltage differencesbetween levels) may result in a relatively low signal-to-noise ratio ofthe read channel, and a relatively high raw bit error rate (RBER).Error-correction code (ECC) (e.g., a low density parity check (LDPC)code) may be used to mitigate read errors.

The use of an LDPC code may involve reading the flash memory multipletimes, which may degrade the performance of the flash memory. Thus,there is a need for a system and method for reading a flash memorymultiple times, while providing good performance.

SUMMARY

Aspects of embodiments of the present disclosure are directed toward asystem and method for adaptive multiple read of NAND flash memory. Asolid state drive may employ adaptive multiple-read to perform enhancedperformance error correction using soft decisions without a performancepenalty that otherwise might result from performing unnecessary reads.The soft decision error correcting algorithm may employ lookup tablescontaining log likelihood ratios. The method may include performing oneor more read operations to obtain one or more raw data words for a codeword, attempting to decode the code words using the one or more raw datawords, and performing additional read operations when the decodingattempt fails. This process may be repeated until a decoding attemptsucceeds.

According to an embodiment of the present invention there is provided amethod for reading data, the method including: performing a first readoperation on a first plurality of flash memory cells, at a firstreference voltage, to form a first raw data word; executing a firsterror correction code decoding attempt with the first raw data word;when the first error correction code decoding attempt succeeds:outputting a decoded data word generated by the first error correctioncode decoding attempt; and when the first error correction code decodingattempt does not succeed: performing a second read operation on thefirst plurality of flash memory cells, at a second reference voltage, toform a second raw data word; and executing a second error correctioncode decoding attempt with the first raw data word and the second rawdata word.

In one embodiment, the performing of the first read operation includesstoring the first raw data word in a buffer, the buffer havingsufficient capacity to store the first raw data word and the second rawdata word.

In one embodiment, the performing of the second error correction codedecoding attempt includes fetching, from a first lookup table, a loglikelihood ratio corresponding to: a bit of the first raw data word; anda corresponding bit of the second raw data word.

In one embodiment, the method includes, when the second error correctioncode decoding attempt succeeds: outputting a decoded data word generatedby the second error correction code decoding attempt; and when thesecond error correction code decoding attempt does not succeed:performing a third read operation on the first plurality of flash memorycells, at a third reference voltage, to form a third raw data word; andexecuting a third error correction code decoding attempt with the firstraw data word, the second raw data word, and the third raw data word.

In one embodiment, the performing of the third error correction codedecoding attempt includes fetching, from a second lookup table, a loglikelihood ratio corresponding to: a bit of the first raw data word; acorresponding bit of the second raw data word; and a corresponding bitof the third raw data word.

In one embodiment, the method includes: performing a third readoperation on a second plurality of flash memory cells, at the firstreference voltage, to form a third raw data word, the second pluralityof flash memory cells being in one page of flash memory with the firstplurality of flash memory cells; and when the first error correctioncode decoding attempt does not succeed: performing a fourth readoperation on the second plurality of flash memory cells, at the secondreference voltage, to form a fourth raw data word.

In one embodiment, the method includes: when the second error correctioncode decoding attempt succeeds: performing a third error correction codedecoding attempt with the third raw data word and the fourth raw dataword.

In one embodiment, the method includes: when the third error correctioncode decoding attempt succeeds: outputting a decoded data word generatedby the third error correction code decoding attempt; and when the thirderror correction code decoding attempt does not succeed: performing afifth read operation on the second plurality of flash memory cells, at athird reference voltage, to form a fifth raw data word; and executing afourth error correction code decoding attempt with the third raw dataword, the fourth raw data word, and the fifth raw data word.

According to an embodiment of the present invention there is provided asolid state drive, including: flash memory; and a processing circuit,the processing circuit being configured to: perform a first readoperation on a first plurality of flash memory cells, at a firstreference voltage, to form a first raw data word; execute a first errorcorrection code decoding attempt with the first raw data word; when thefirst error correction code decoding attempt succeeds: output a decodeddata word generated by the first error correction code decoding attempt;and when the first error correction code decoding attempt does notsucceed: perform a second read operation on the first plurality of flashmemory cells, at a second reference voltage, to form a second raw dataword; and execute a second error correction code decoding attempt withthe first raw data word and the second raw data word.

In one embodiment, the performing of the first read operation includesstoring the first raw data word in a buffer, the buffer havingsufficient capacity to store the first raw data word and the second rawdata word.

In one embodiment, the performing of the second error correction codedecoding attempt includes fetching, from a first lookup table, a loglikelihood ratio corresponding to: a bit of the first raw data word; anda corresponding bit of the second raw data word.

In one embodiment, the processing circuit is further configured to: whenthe second error correction code decoding attempt succeeds: output adecoded data word generated by the second error correction code decodingattempt; and when the second error correction code decoding attempt doesnot succeed: perform a third read operation on the first plurality offlash memory cells, at a third reference voltage, to form a third rawdata word; and execute a third error correction code decoding attemptwith the first raw data word, the second raw data word, and the thirdraw data word.

In one embodiment, the performing of the third error correction codedecoding attempt includes fetching, from a second lookup table, a loglikelihood ratio corresponding to: a bit of the first raw data word; acorresponding bit of the second raw data word; and a corresponding bitof the third raw data word.

In one embodiment, the processing circuit is further configured to:perform a third read operation on a second plurality of flash memorycells, at the first reference voltage, to form a third raw data word,the second plurality of flash memory cells being in one page of flashmemory with the first plurality of flash memory cells; and when thefirst error correction code decoding attempt does not succeed: perform afourth read operation on the second plurality of flash memory cells, atthe second reference voltage, to form a fourth raw data word.

In one embodiment, the processing circuit is further configured to: whenthe second error correction code decoding attempt succeeds: perform athird error correction code decoding attempt with the third raw dataword and the fourth raw data word.

In one embodiment, the processing circuit is further configured to: whenthe third error correction code decoding attempt succeeds: output adecoded data word generated by the third error correction code decodingattempt; and when the third error correction code decoding attempt doesnot succeed: perform a fifth read operation on the second plurality offlash memory cells, at a third reference voltage, to form a fifth rawdata word; and execute a fourth error correction code decoding attemptwith the third raw data word, the fourth raw data word, and the fifthraw data word.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the present invention will beappreciated and understood with reference to the specification, claims,and appended drawings wherein:

FIG. 1A is a block diagram of a host computer and a solid state drive,according to an embodiment of the present invention;

FIG. 1B is a graph of probability density functions, according to anembodiment of the present invention;

FIG. 2 is a block diagram of a system for performing adaptive multiplereads, according to an embodiment of the present invention;

FIG. 3 is a flow chart of a method for performing adaptive multiplereads, according to an embodiment of the present invention;

FIG. 4 is a flow chart of a method for performing adaptive multiplereads, according to an embodiment of the present invention;

FIG. 5A is a flow chart of a method for performing adaptive multiplereads, according to an embodiment of the present invention; and

FIG. 5B is a flow chart of a method for performing adaptive multiplereads, according to an embodiment of the present invention.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appendeddrawings is intended as a description of exemplary embodiments of asystem and method for adaptive multiple read of NAND flash provided inaccordance with the present invention and is not intended to representthe only forms in which the present invention may be constructed orutilized. The description sets forth the features of the presentinvention in connection with the illustrated embodiments. It is to beunderstood, however, that the same or equivalent functions andstructures may be accomplished by different embodiments that are alsointended to be encompassed within the spirit and scope of the invention.As denoted elsewhere herein, like element numbers are intended toindicate like elements or features.

Referring to FIG. 1A, in some embodiments a solid state drive 110 may,in operation, be connected to, and provide storage for, a host 115,e.g., a server or other computer. The host interface (including the hostconnector, and the communications protocols) between the solid statedrive 110 and the host may be, for example, a storage interface such asSerial Advanced Technology Attachment (SATA), Fibre Channel, SmallComputer System Interface (SCSI), Serial Attached SCSI (SAS), PeripheralComponent Interconnect Express (PCIe), Non Volatile Memory Express(NVMe), SCSI over PCIe, or a more general-purpose interface such asEthernet or Universal Serial Bus (USB). In some embodiments, the solidstate drive 110 may conform to a 3.5 inch hard drive form-factor (or“large form factor” (LFF)) standard, or it may conform to a 2.5 inchhard drive form-factor (or small form factor (SFF)) standard. In otherembodiments the solid state drive 110 may conform to a standard PCIecard form factor, e.g., a full-height, full length (FH-FL) card outline,or a full-height, half length (FH-HL) outline. The solid state drive 110may include a controller, buffer memory, and flash memory. Thecontroller may execute software and/or firmware, stored, for example, inthe buffer memory, or in read-only memory in the controller (or separatefrom the controller).

The flash memory may include a plurality of cells, each including atransistor with a floating gate. The cell may be programmed by a processthat stores charge on the floating gate. The transistor includes anadditional control gate, or “word line control gate” on top of thefloating gate. When a voltage is applied to the word line control gate,the state of the transistor (whether on (e.g., conducting) or off (e.g.,not conducting) depends both on the amount of charge stored on thefloating gate, and on the voltage (or “word line voltage”, or “referencevoltage”) applied to the word line control gate. Accordingly, thethreshold voltage (i.e., the reference voltage at which the transistortransitions between the on state and the off state) depends on theamount of charge stored on the floating gate. The amount of chargestored on the floating gate may be used to store information. Forexample, in a single level cell (SLC), a large negative charge mayrepresent 0 (or “0” or “logical 0”) and a smaller negative charge or nonegative charge may represent 1 (or “1” or “logical 1”). In amulti-level cell (MLC), four different states, each corresponding to adifferent amount of charge stored on the floating gate may be used tostore two bits, and in a Triple Level Cell (TLC)) eight different statesmay be used to store three bits.

The flash memory cell may be read by applying the reference voltage tothe word line control gate and determining, using a sense amplifiercomparator, whether the transistor is on or off. The reference voltagemay be adjustable in increments of a reference voltage step size (e.g.,1 mV), which may be a characteristic of a readout circuit in (andfabricated with) the flash memory device. After the cell is programmed,the amount of charge stored on the floating gate may change gradually,resulting, on occasion, in a difference between a logical value (or “bitvalue”) that was written to the cell and a bit value that is read fromthe cell. Such a difference may be referred to as a “bit flip”. Whethera bit is flipped in a cell may depend on the reference voltage used toread the cell; in general, a bit may flip if the change in the amount ofcharge stored on the floating gate causes the threshold voltage to movefrom one side of the reference voltage to the other side of thereference voltage (e.g., causes the threshold voltage to change frombeing less than the reference voltage to being greater than thereference voltage). Error correcting codes may be used to correct errorsresulting from bit flips. Such error correcting codes may use, as input,a quantity of data (i.e., a number of bits) referred to herein as a“code word”.

In some embodiments, a plurality of flash memory cells may be readmultiple times with multiple different values of the reference voltage(i.e., the voltage applied to the word line of the flash memory cells).Each reference voltage may be selected from a set of available referencevoltages (e.g., voltages generated by a set of voltage sources, or by ananalog to digital converter). After each read operation, the results,i.e., the raw data, may be fed to an error correcting code block whichmay attempt to decode the raw data (i.e., to correct any errors in theraw data). If the decoding attempt succeeds, the decoded data may, e.g.,be delivered to the host. If the decoding attempt fails, an additionalread operation may be performed, with another value of the referencevoltage. This process, in which additional read operations are performeduntil error decoding succeeds, may be referred to as “adaptivemulti-read”. In this manner, the spending of time performing a thirdread operation may be avoided, for example, when after a second readoperation, sufficient information has been obtained to perform asuccessful decoding operation.

Each decoding attempt may employ a lookup table (LUT) including an entryfor each possible outcome for the set of read operations performed.During each read operation, the corresponding voltage may be applied tothe word line, and a sense amplifier comparator may generate an outputcorresponding to, e.g., logical 1 if the flash cell transistor turns onat the current reference voltage, and logical 0 if it does not.Accordingly, the threshold voltage of the flash cell may be inferred tofall into one of a plurality of regions each bounded by one or tworeference voltages. For example, in FIG. 1B, if read operations areperformed with each of three available reference voltage values ofV_(T)., V_(T), and V_(T+), then, given the results of the readoperations, the threshold voltage may be inferred to be in one of fourregions, labelled A, B, C, and D in FIG. 1B, and correspondingrespectively to threshold voltage values that are (i) less than V_(T). ,(ii) greater than V_(T), and less than V_(T), (iii) greater than V_(T)and less than and V_(T+), and (iv) greater than V_(T+). The read resulttable 150 of FIG. 1B shows the result of each of the read operations foreach of these four cases. For example, if the threshold voltage is inregion B, then the three read operations (with reference voltages ofV_(T)., V_(T), and V_(T+)) may generate raw data of {0 1 1}, as shown inthe second column of the read result table 150. As used herein, a listof binary digits between brace brackets (e.g., {0 1 1}) represents asequence of raw bits obtained from multiple read operations performed atrespective reference voltages of a corresponding sequence of referencevoltages.

The input to an error correcting decoder using soft decision values mayinclude a log likelihood ratio (LLR) for each cell. The log likelihoodratio may be defined as log(P(0)/P(1)) (where “log”, without asubscript, refers to the natural logarithm) where P(0) is theprobability of “0” being the bit that was written to the cell and P(1)is the probability of “1” being the bit that was written to the cell.This log likelihood ratio may be obtained from a lookup table that hasone entry for each of the regions, e.g., four entries, corresponding tothe regions A, B, C, and D of FIG. 1B. If adaptive multi-read isemployed, several lookup tables may be present, one for eachuser-defined combination of read operations (e.g., one for eachuser-defined read sequence). For example, a first read operation may beperformed with a reference voltage of V_(T), resulting in a 1 if thethreshold voltage is in region A or B and a 0 if the threshold voltageis in region C or D. A first lookup table, corresponding to this firstread operation, may then have two entries, one being the log likelihoodratio for a threshold voltage less than V_(T) (corresponding to regionsA and B) and the other being the log likelihood ratio for a thresholdvoltage greater than V_(T) (corresponding to regions C and D).

A second lookup table may contain log likelihood ratios for, forexample, the three possible results after a first read operation with athreshold voltage of V_(T), and a second read operation with a thresholdvoltage of V_(T−). A third lookup table may contain log likelihoodratios for the four possible results after a first read operation with athreshold voltage of V_(T), a second read operation with a thresholdvoltage of V_(T)., and a third read operation with a threshold voltageof V_(T+). Although FIG. 1B illustrates an exemplary embodimentutilizing three different reference voltages; other embodiments may usefewer or more different reference voltages (e.g., five differentreference voltages).

Performing a larger number of read operations on each cell may result inan increased likelihood of successful decoding, but it may also resultin a reduction in performance, e.g., an increase in the time taken tocomplete the execution of a read command. For example, each readoperation may take about 50 microseconds (50 us) for a 2-bit/cell MLC,and more than 100 us for a 3-bit/cell TLC. Moreover, read operations atdifferent reference voltages within one page of flash memory may beconstrained to be performed at only one reference voltage at a time. Assuch, considerable performance improvements may be achieved by avoidingread operations that are not necessary for successful decoding (e.g., byomitting a third read operation when after two read operationssuccessful decoding is already possible).

FIG. 2 is a block diagram of an adaptive multiple-read system for NANDflash, in some embodiments. The adaptive multiple-read system includesan intermediate buffer 210, a NAND flash memory array 220, a centralprocessing unit (CPU) subsystem 230 and an error correcting code (ECC)subsystem 240. The central processing unit (CPU) subsystem 230 and theerror correcting code (ECC) subsystem 240 may be part of the solid statedrive controller. The ECC subsystem 240 includes a plurality of lookuptables 255, for looking up soft decision values, e.g., log likelihoodratios, as mentioned above. For example, the lookup table for athree-read case (as illustrated in FIG. 1B) may translate the pattern {11 1} to the soft-decision value S30, it may translate the pattern {0 11} to the soft-decision value S31, it may translate the pattern {0 0 1}to the soft-decision value S32, and it may translate the pattern {0 0 0}to the soft-decision value S33. For a two-read case the lookup table maytranslate the pattern {1 1} to the soft-decision value S20, it maytranslate the pattern {0 1} to the soft-decision value S21, and it maytranslate the pattern {0 0} to the soft-decision value S22.

For a four-read case, the lookup table may translate the pattern {1 1 11} to the soft-decision value S40, it may translate the pattern {0 1 11} to the soft-decision value S41, it may translate the pattern {0 0 11} to the soft-decision value S42, it may translate the pattern {0 0 01} to the soft-decision value S43, and it may translate the pattern {0 00 0} to the soft-decision value S44. The lookup tables may be programmedwith data from a NAND flash channel calibration phase (as described, forexample, in the ‘075 Application) or from a firmware and/or softwarecalculation using a pre-defined flash channel model. Each soft-decisionvalue may be a log likelihood ratio, as mentioned above.

The execution of a read command may then be adaptive. For example, afterone or more read operations have been performed, a decoding attempt maybe made, and, if the decoding attempt fails, additional read operationsmay be performed and another decoding attempt may be made.

For example, in some embodiments, a first read operation, which may bereferred to as RDO, may be performed (through the flash channelinterface 295) at a first reference voltage, and a raw data wordcorresponding to code word 0 (cw0 in FIG. 2) may be stored in acorresponding code word buffer 270 of the intermediate buffer 210. Thiscode word may then be transferred from the intermediate buffer 210 to alocal code word buffer 260 in the ECC subsystem 240. An LDPC decoder 250may then attempt to decode the code word, using the lookup table for theone-read case, from among the set of lookup tables 255. If the decodingattempt succeeds, the system may output (or store for future output) thedecoded code word. If the decoding attempt fails, the ECC subsystem 240notifies the firmware via an internal communication system 290. Thefirmware executing in the CPU subsystem 230 then executes a second readoperation (RD1), at a different reference voltage, the raw data wordfrom which is saved in another code word buffer of the intermediatebuffer 210 (and copied into another local code word buffer in the ECCsubsystem 240). The LDPC decoder 250 then attempts again to decode thecode word, this time using the respective raw data words from the firstand second read operations, and the lookup table for the two-read case.If the decoding attempt succeeds, the system may output (or store forfuture output) the decoded code word. If the decoding attempt fails,additional read operations and decoding attempts may be made until adecoding attempt succeeds, or until failure is declared (at which pointa RAID recovery may be used (where the RAID is a redundant array ofindependent disks of which the solid state drive 110 is a member).

Code words stored together in one flash page (i.e., in the same page offlash memory) may have similar histories and the smallest number of readoperations resulting in a successful decoding attempt may be the samefor all of them. Accordingly, as illustrated in FIG. 3, a plurality ofcode words (e.g., n code words) within a page may be read one or moretimes, with the number of read operations being adapted to allowsuccessful decoding of a first code word (e.g., cw0) from among theplurality of code words. The remainder of the code words in the page maythen also be decoded, using the raw data words already read. In act 310,a reference voltage is set, in act 320, a read operation is performed atthe reference voltage, in act 330, the raw data word from the readattempt is sent to the ECC subsystem, and in act 340, a decoding attemptis made. As described above, this process is repeated until a decodingattempt of the first code word succeeds. In act 360 the raw data wordsfrom the same read operations for the i^(th) code word (i.e., the secondcode word, the third code word, etc.) are sent to the ECC subsystem 240,and used, in an act 370, in a decoding attempt. Acts 360 and 370 maythen be repeated until there are (as determined in act 380) no more codewords to be decoded, from within the same page as the first code word.

Referring to FIG. 4, in another embodiment, the method of FIG. 3 ismodified in two respects. First, as illustrated in acts 410, 420, and425, the process may perform a minimum, or “base” number of reads beforeperforming the first decoding attempt on the first code word (cw0).Second, during the decoding of the remaining code words (after the firstcode word has been successfully decoded), if one of the decodingattempts fails (as determined in act 480) the system may performadditional read operations. In this embodiment, the base number of readsis programmable by the firmware.

FIGS. 5A and 5B show a method of adaptive multiple read operation,according to one embodiment. The method includes a single read ECCdecoding portion 520 and an adaptive multiple read decoding portion 510,details of which are shown in FIG. 5B. In FIG. 5A, if a mis-correction(“Mis-Corr.”) is detected (e.g., as a result of a cyclic redundancycheck (CRC) failure), the system may execute one or more additionalone-read read operations and decoding attempts, with the referencevoltage set to one or more respective different values. After successfuldecoding attempts statistical information may be collected (e.g., bycomparing the raw data words and the decoded code words) to assist, forexample, in selecting reference voltage levels for future readoperations. For example, if it is determined that the number of bitflips at the first read operation has an imbalance (e.g., there beingmore 0-to-1 bit flips than 1-to-0 bit flips) then the reference voltageused for the first read operation may be increased or decreased (e.g.,by one increment of the reference voltage step size) so as to reduce theimbalance. FIGS. 5A and 5B illustrate an embodiment with up to 4additional read operations in the adaptive multiple read decodingportion 510 of FIG. 5B; in other embodiments there may be more or feweradditional read operations available in the adaptive multiple readdecoding portion 510.

Similarly, other reference voltages used for second, or third (or later)read operations may be adjusted so that (i) they are sufficientlydifferent from other reference voltages to result in different raw datawords than those already read and (ii) they are not sufficiently extremeto result in raw data words that differ excessively from those obtainedfor adjacent reference voltages. These criteria may be used toautomatically adjust the reference voltages or to find, empirically, aset of reference voltages that provides acceptable performance.Reference voltages may be uniformly spaced (e.g., each being separatedfrom the others by a set multiple of the reference voltage step size) orthey may be non-uniformly spaced (in the latter case a table may be usedto specify the reference voltages, in units of the reference voltagestep size). The table used to set the initial reference voltage (andthat may be used to set subsequent reference voltages) may be generatedfrom data on the characteristics of the flash memory cells; such datamay be provided by the manufacturer of the flash memory devices and/orgenerated from the collected statistics. The table may have multipleentries for each reference voltage, the different entries correspondingto different cell ages (measured, e.g., by the number of program/erasecycles). In operation, it may be the case that multiple read operationsare rarely used to execute a read command, and the control logic may bea single-thread design, i.e., decoding operations are processed one at atime. Although some embodiments are described herein as using an LDPCerror correcting code, the invention is not limited thereto, and theerror correcting code may be any error correcting code which can takesoft information.

In light of the foregoing, a solid state drive may employ adaptivemultiple-read to perform enhanced performance error correction usingsoft decisions without a performance penalty that otherwise might resultfrom performing unnecessary read operations. The soft decision errorcorrecting algorithm may employ lookup tables containing log likelihoodratios. The method may include performing one or more read operations toobtain one or more raw data words for a code word, attempting to decodethe code words using the one or more raw data words, and performingadditional read operations when the decoding attempt fails. This processmay be repeated until a decoding attempt succeeds.

Various processing operations described above may be performed by thecontroller of the solid state drive 110. The controller may be aprocessing circuit. The term “processing circuit” is used herein toinclude any combination of hardware, firmware, and software, employed toprocess data or digital signals. Processing circuit hardware mayinclude, for example, application specific integrated circuits (ASICs),general purpose or special purpose central processing units (CPUs),digital signal processors (DSPs), graphics processing units (GPUs), andprogrammable logic devices such as field programmable gate arrays(FPGAs). In a processing circuit, as used herein, each function isperformed either by hardware configured, i.e., hard-wired, to performthat function, or by more general purpose hardware, such as a CPU,configured to execute instructions stored in a non-transitory storagemedium. A processing circuit may be fabricated on a single printedcircuitboard (PCB) or distributed over several interconnected PCBs. Aprocessing circuit may contain other processing circuits; for example aprocessing circuit may include two processing circuits, an FPGA and aCPU, interconnected on a PCB.

It will be understood that, although the terms “first”, “second”,“third”, etc., may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer or section from another element, component, region, layer orsection. Thus, a first element, component, region, layer or sectiondiscussed below could be termed a second element, component, region,layer or section, without departing from the spirit and scope of theinventive concept.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcept. As used herein, the terms “substantially,” “about,” and similarterms are used as terms of approximation and not as terms of degree, andare intended to account for the inherent deviations in measured orcalculated values that would be recognized by those of ordinary skill inthe art.

As used herein, the singular forms “a” and “an” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising”, when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof. As used herein, the term “and/or”includes any and all combinations of one or more of the associatedlisted items. Expressions such as “at least one of,” when preceding alist of elements, modify the entire list of elements and do not modifythe individual elements of the list. Further, the use of “may” whendescribing embodiments of the inventive concept refers to “one or moreembodiments of the present invention”. Also, the term “exemplary” isintended to refer to an example or illustration. As used herein, theterms “use,” “using,” and “used” may be considered synonymous with theterms “utilize,” “utilizing,” and “utilized,” respectively.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to”, “coupled to”, or “adjacent to” anotherelement or layer, it may be directly on, connected to, coupled to, oradjacent to the other element or layer, or one or more interveningelements or layers may be present. In contrast, when an element or layeris referred to as being “directly on”, “directly connected to”,“directly coupled to”, or “immediately adjacent to” another element orlayer, there are no intervening elements or layers present.

Any numerical range recited herein is intended to include all sub-rangesof the same numerical precision subsumed within the recited range. Forexample, a range of “1.0 to 10.0” is intended to include all subrangesbetween (and including) the recited minimum value of 1.0 and the recitedmaximum value of 10.0, that is, having a minimum value equal to orgreater than 1.0 and a maximum value equal to or less than 10.0, suchas, for example, 2.4 to 7.6. Any maximum numerical limitation recitedherein is intended to include all lower numerical limitations subsumedtherein and any minimum numerical limitation recited in thisspecification is intended to include all higher numerical limitationssubsumed therein.

Although exemplary embodiments of a system and method for adaptivemultiple read of NAND flash have been specifically described andillustrated herein, many modifications and variations will be apparentto those skilled in the art. Accordingly, it is to be understood that asystem and method for adaptive multiple read of NAND flash constructedaccording to principles of this invention may be embodied other than asspecifically described herein. The invention is also defined in thefollowing claims, and equivalents thereof

What is claimed is:
 1. A method for reading data, the method comprising:performing a first read operation on a first plurality of flash memorycells, at a first reference voltage, to form a first raw data word;executing a first error correction code decoding attempt with the firstraw data word; when the first error correction code decoding attemptsucceeds: outputting a decoded data word generated by the first errorcorrection code decoding attempt; and when the first error correctioncode decoding attempt does not succeed: performing a second readoperation on the first plurality of flash memory cells, at a secondreference voltage, to form a second raw data word; and executing asecond error correction code decoding attempt with the first raw dataword and the second raw data word.
 2. The method of claim 1, wherein theperforming of the first read operation comprises storing the first rawdata word in a buffer, the buffer having sufficient capacity to storethe first raw data word and the second raw data word.
 3. The method ofclaim 1, wherein the performing of the second error correction codedecoding attempt comprises fetching, from a first lookup table, a loglikelihood ratio corresponding to: a bit of the first raw data word; anda corresponding bit of the second raw data word.
 4. The method of claim1, further comprising, when the second error correction code decodingattempt succeeds: outputting a decoded data word generated by the seconderror correction code decoding attempt; and when the second errorcorrection code decoding attempt does not succeed: performing a thirdread operation on the first plurality of flash memory cells, at a thirdreference voltage, to form a third raw data word; and executing a thirderror correction code decoding attempt with the first raw data word, thesecond raw data word, and the third raw data word.
 5. The method ofclaim 4, wherein the performing of the third error correction codedecoding attempt comprises fetching, from a second lookup table, a loglikelihood ratio corresponding to: a bit of the first raw data word; acorresponding bit of the second raw data word; and a corresponding bitof the third raw data word.
 6. The method of claim 1, furthercomprising: performing a third read operation on a second plurality offlash memory cells, at the first reference voltage, to form a third rawdata word, the second plurality of flash memory cells being in one pageof flash memory with the first plurality of flash memory cells; and whenthe first error correction code decoding attempt does not succeed:performing a fourth read operation on the second plurality of flashmemory cells, at the second reference voltage, to form a fourth raw dataword.
 7. The method of claim 6, further comprising: when the seconderror correction code decoding attempt succeeds: performing a thirderror correction code decoding attempt with the third raw data word andthe fourth raw data word.
 8. The method of claim 7, further comprising:when the third error correction code decoding attempt succeeds:outputting a decoded data word generated by the third error correctioncode decoding attempt; and when the third error correction code decodingattempt does not succeed: performing a fifth read operation on thesecond plurality of flash memory cells, at a third reference voltage, toform a fifth raw data word; and executing a fourth error correction codedecoding attempt with the third raw data word, the fourth raw data word,and the fifth raw data word.
 9. A solid state drive, comprising: flashmemory; and a processing circuit, the processing circuit beingconfigured to: perform a first read operation on a first plurality offlash memory cells, at a first reference voltage, to form a first rawdata word; execute a first error correction code decoding attempt withthe first raw data word; when the first error correction code decodingattempt succeeds: output a decoded data word generated by the firsterror correction code decoding attempt; and when the first errorcorrection code decoding attempt does not succeed: perform a second readoperation on the first plurality of flash memory cells, at a secondreference voltage, to form a second raw data word; and execute a seconderror correction code decoding attempt with the first raw data word andthe second raw data word.
 10. The solid state drive of claim 9, whereinthe performing of the first read operation comprises storing the firstraw data word in a buffer, the buffer having sufficient capacity tostore the first raw data word and the second raw data word.
 11. Thesolid state drive of claim 9, wherein the performing of the second errorcorrection code decoding attempt comprises fetching, from a first lookuptable, a log likelihood ratio corresponding to: a bit of the first rawdata word; and a corresponding bit of the second raw data word.
 12. Thesolid state drive of claim 9, wherein the processing circuit is furtherconfigured to: when the second error correction code decoding attemptsucceeds: output a decoded data word generated by the second errorcorrection code decoding attempt; and when the second error correctioncode decoding attempt does not succeed: perform a third read operationon the first plurality of flash memory cells, at a third referencevoltage, to form a third raw data word; and execute a third errorcorrection code decoding attempt with the first raw data word, thesecond raw data word, and the third raw data word.
 13. The solid statedrive of claim 12, wherein the performing of the third error correctioncode decoding attempt comprises fetching, from a second lookup table, alog likelihood ratio corresponding to: a bit of the first raw data word;a corresponding bit of the second raw data word; and a corresponding bitof the third raw data word.
 14. The solid state drive of claim 9,wherein the processing circuit is further configured to: perform a thirdread operation on a second plurality of flash memory cells, at the firstreference voltage, to form a third raw data word, the second pluralityof flash memory cells being in one page of flash memory with the firstplurality of flash memory cells; and when the first error correctioncode decoding attempt does not succeed: perform a fourth read operationon the second plurality of flash memory cells, at the second referencevoltage, to form a fourth raw data word.
 15. The solid state drive ofclaim 14, wherein the processing circuit is further configured to: whenthe second error correction code decoding attempt succeeds: perform athird error correction code decoding attempt with the third raw dataword and the fourth raw data word.
 16. The solid state drive of claim15, wherein the processing circuit is further configured to: when thethird error correction code decoding attempt succeeds: output a decodeddata word generated by the third error correction code decoding attempt;and when the third error correction code decoding attempt does notsucceed: perform a fifth read operation on the second plurality of flashmemory cells, at a third reference voltage, to form a fifth raw dataword; and execute a fourth error correction code decoding attempt withthe third raw data word, the fourth raw data word, and the fifth rawdata word.